
`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////
////                                                              //// 
////                                                              //// 
////  Part of the project chess controller                        ////  
////                                                              ////
////                                                              //// 
////  Description                                                 //// 
////   - Comunicacion y verificacion                              //// 
////                                                              //// 
////  To Do:                                                      //// 
////   -                                                          //// 
////                                                              //// 
////  Author(s):                                                  //// 
////      - Sergio Gonzalez Q, sergiogq@hotmail.es                ////
////      - Alejandro Morales A, ale3191@gmail.com                //// 
////                                                              //// 
////////////////////////////////////////////////////////////////////// 
////                                                              //// 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 //// 
////                                                              //// 
//// This source file may be used and distributed without         //// 
//// restriction provided that this copyright statement is not    //// 
//// removed from the file and that any derivative work contains  //// 
//// the original copyright notice and the associated disclaimer. //// 
////                                                              //// 
//// This source file is free software; you can redistribute it   //// 
//// and/or modify it under the terms of the GNU Lesser General   //// 
//// Public License as published by the Free Software Foundation; //// 
//// either version 2.1 of the License, or (at your option) any   //// 
//// later version.                                               //// 
////                                                              //// 
//// This source is distributed in the hope that it will be       //// 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   //// 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //// 
//// PURPOSE.  See the GNU Lesser General Public License for more //// 
//// details.                                                     //// 
////                                                              //// 
//// You should have received a copy of the GNU Lesser General    //// 
//// Public License along with this source; if not, download it   //// 
//// from http://www.opencores.org/lgpl.shtml                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////

// Modulo principal que comunica todos los modulos encargados de la comunicacion
// serial como de la verificacion de los movimientos de las piezas 

module chess_game( 
	input _clk_i, 
	input _rst_i,
	input rx_i,
	input row0_i, row1_i, row2_i, row3_i, row4_i, row5_i, row6_i, row7_i,
	output tx_o,
	output [7:0] columnLED_o,
	output  [3:0]  seleccion7seg_o,
	output  [7:0]  out_o,
	output [7:0] column_o,
	output failed_o, failed_color_o, gamer_o,led_o
    );

	 wire send_data_i;
	 wire data_sent_o;
	 wire [63:0] chessboard_snapshot_i;
	 wire _250Hz_clk;
	 wire [2:0] row, column;
	 wire [3:0] pos;
	 wire empty, uart_clk;
	 
	 
	// Instanciacin del mdulo divisor de la frecuencia de reaccion de la SRAM
SystemClockDivider fsm_clk (
	 ._clk_i(_clk_i),
	 ._rst_i(_rst_i),
	 .divided_freq_o(_250Hz_clk)
	 );

// instanciacion de modulo encargado de la verifiacion de los movimoentos
chess_controller controller(
	._ckl_i(_clk_i),
	._rst_i(_rst_i),
	.pos_i(pos),
	.empty_i(empty),
	.sampling_time_i(_250Hz_clk),
	.failed_color_o(failed_color_o),
	.failed_o(failed_o),
	.gamer_o(gamer_o),
	.led_o(led_o)
	);
	
// Instancia la maquina responsable de la lectura del tablero
FSM_Board_Reader fsm (
    ._rst_i(_rst_i), 
    ._system_clk_i(_clk_i), 
	 ._board_checking_clk_i(_250Hz_clk),
    .data_sent_i(data_sent_o), 
    .chessboard_snapshot_o(chessboard_snapshot_i), 
    .send_data_o(send_data_o),
	 .row0_i(row0_i), .row1_i(row1_i), .row2_i(row2_i), .row3_i(row3_i), 
	 .row4_i(row4_i), .row5_i(row5_i), .row6_i(row6_i), .row7_i(row7_i),
	 .column_o(column_o),
	 .columnLED_o(columnLED_o),
	 .columnCounter_o(column),
	 .rowCounter_o(row),
	 .pos_o(pos),
	 .empty_o(empty)
    );

// modulo encargado de las luces
SevenSegmentDisplayController cntrl(
		._clk_i(_clk_i),
		.row_i(row),
		.column_i(column),
		._rst_i(_rst_i),
		.seleccion7seg_o(seleccion7seg_o),
		.out_o(out_o)
     );
	  
// Instancia la fachadad que une la comunicacion serial
Facade facade (
    ._clk_i(_clk_i), 
    ._rst_i(_rst_i), 
    .chessboard_snapshot_i(chessboard_snapshot_i), 
    .send_data_i(send_data_o), 
    .data_sent_o(data_sent_o), 
    .uart_clk(uart_clk), 
    .tx_o(tx_o), 
    .rx_i(rx_i)
    );

endmodule

